Area and Power optimisation for AES encryption module implementation on FPGA

Ubiquitous computing has been getting deployed into many applications in daily life. However, one of the difficulties to make it reliable is the lack of security. The constraints of area and power are the challenges for the cryptographic algorithms to be implemented. In this paper, the implementation of Advanced Encryption Standard (AES) encryption algorithm is proposed in terms of resource and power optimisation. The design is based on a 8-bit architecture and implemented on Altera Cyclone II EP2C672C6. The proposed design exhibits 272 LEs and takes 5.88 mW of power which is an improvement in comparison with other published works.