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Area and Power optimisation for AES encryption module implementation on FPGA

PHAM, Tuan Anh, HASAN, Mohammad and YU, Hongnian (2012) Area and Power optimisation for AES encryption module implementation on FPGA. In: The 18th International Conference on Automation and Computing, 08 Sep 2012, Loughborough, UK.

DSM2_AES_Implementation v4 - submitted.pdf

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Abstract or description

Ubiquitous computing has been getting deployed into many applications in daily life. However, one of the difficulties to make it reliable is the lack of security. The constraints of area and power are the challenges for the cryptographic algorithms to be implemented. In this paper, the implementation of Advanced Encryption Standard (AES) encryption algorithm is proposed in terms of resource and power optimisation. The design is based on a 8-bit architecture and implemented on Altera Cyclone II EP2C672C6. The proposed design exhibits 272 LEs and takes 5.88 mW of power which is an improvement in comparison with other published works.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: AES-128 encryption, embedded system, FPGA, resource-limited application
Subjects: G400 Computer Science
Faculty: Previous Faculty of Computing, Engineering and Sciences > Computing
Depositing User: Mohammad HASAN
Date Deposited: 02 May 2013 22:44
Last Modified: 02 May 2013 22:44

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